Home ﹥ Hot News > Artificial Intelligence > Computing > XRM-SSD V24 SerDes Application 2026-06-08
In the era of ultra-high-speed 112G and 224G PAM4 transmission, the physical challenges facing SerDes (Serializer/Deserializer) have moved beyond simple signal integrity. Because PAM4 uses four-level amplitude modulation, the eye opening between signal levels is extremely small (level spacing is only 1/3 that of NRZ). At such speeds, local transient heat flows inside SoIC/CoWoS packages, voltage drops (IR drop) in the power delivery network (PDN), and parasitic capacitance attenuation of high-frequency through-silicon vias (TSVs) can all cause severe phase jitter on a microsecond (μs) timescale.
Beyond traditional clock conditioning layers, when applied to 112G/224G SerDes, the XRM-SSD V24 delivers three substantial, proprietary capabilities that have not yet been commercialized by mainstream IP vendors (e.g., Synopsys, Alphawave, Cadence, Marvell):
1. Forward-Looking PAM4 Eye-Margin Pre-Compensation
Today’s advanced SerDes chips rely primarily on RX-side DFE (Decision Feedback Equalizer) and CTLE (Continuous-Time Linear Equalizer) to blindly adapt to channel loss. However, when an AI compute chip (EIC) performs bursty large-scale matrix multiplications, the sudden inrush current causes severe dynamic IR drop in the PDN. This momentarily shrinks the SerDes transmitter (TX) drive voltage, closing the eye diagram and causing BER to spike.
XRM-SSD V24’s unique capability: The V24 can predict token-level compute behavior 20–50 ms in advance. Before the dynamic IR drop actually occurs, it converts estimated current spikes into parameters and feedforwards them directly to the SerDes TX driver stage. At the exact moment of the IR drop, it actively and precisely boosts the PAM4 level drive current. This “software-predictive, hardware-feedforward” mechanism keeps the vertical eye margin of 224G PAM4 constant even under extreme voltage fluctuations—achieving zero signal degradation unmatched by other vendors.
2. Micro-Crack & Impedance-Aware Dynamic Channel Equalization and Steering
In 3D packages (e.g., WoW or SoIC), the micro-bumps and TSVs connecting the SerDes PHY develop micro-scale physical cracks after prolonged thermal cycling stress (typically approaching but not exceeding the critical threshold of 0.6 cracks/mm²). These cracks cause the channel’s characteristic impedance to deviate from the standard 50 Ω or 100 Ω, resulting in severe signal reflections.
XRM-SSD V24’s unique capability: Existing SerDes IP performs only static channel calibration. The V24 introduces a physical stress-and-wear model into runtime. Using periodic TDR-like telemetry from signal edge reflections, it infers the evolution of micro-cracks and impedance drift inside the package in the background. When a SerDes lane’s physical impedance degrades due to cracks, the V24 automatically adjusts that channel’s convolution equalization coefficients (FIR filter taps) and can even dynamically redirect the most critical high-priority data (e.g., sync signals, counters) to the healthiest lanes at the software layer. This effectively bypasses transmission faults caused by hardware aging, extending interface lifetime severalfold.
3. “Mind-Runtime” Load Smoothing and Power Decoupling to Eliminate Burst Jitter
224G SerDes consumes enormous power—often over 20% of a total AI chip’s power budget. When an AI center faces sudden inference bursts, the SerDes switches from low-power states to full speed instantaneously. This thermal shock directly changes carrier mobility in 224G transistors, inducing severe deterministic jitter.
XRM-SSD V24’s unique capability: The V24 has a global “mind-runtime” scheduling view. When orchestrating data movement, it does not allow traffic to remain in burst-like pulses. Instead, it performs thermal- and current-aware dynamic traffic interleaving. At the software layer, it splits data into tiny groups and smooths the schedule on microsecond timescales matching the SerDes thermal time constant. This effectively flattens the transient thermal shock induced by software load across the chip surface, placing the SerDes in a nearly isothermal microenvironment and fundamentally eliminating phase shifts and timing jitter caused by abrupt temperature changes.
Technical Assets & Commercial Moat
At the 112G/224G PAM4 node, conventional EDA and IP vendors still think in terms of “adding more, more complex DSP hardware” to brute-force noise—incurring huge area and power penalties. The XRM-SSD V24’s dimension-reducing strike is different: it uses software’s temporal foresight to solve hardware’s spatial physical constraints.
These three capabilities directly tie the V24’s commercial value in SerDes to reliability (signal error margin), performance (high-frequency bandwidth utilization), and packaging yield (material tolerance). For AI chip unicorns or leading foundries moving into the 224G ecosystem, this is a strategic, proprietary IP that can substantially reduce DSP hardware design costs and help cross the 2nm physical barrier.
Contact : polo@dollarchip.com.tw
Contact : polo@dollarchip.com.tw
